Multi-dimensional coding for error reduction

ABSTRACT

A stream of binary bits is converted into blocks of eight parallel bits. A first group of five of the eight bits addresses a memory device which has thirty-two code words each having four numbers representing the coordinates of signal points in four-dimensional space. The remaining three of the eight bits are expanded to four bits by a convolutional encoder having three bits of memory. These four bits are then used to multiply the four numbers of a code word read out from the memory device. This method permits a block of eight binary bits to be coded into any one of five hundred and twelve four-dimensional code words.

TECHNICAL FIELD

This invention relates to coding information so as to reduce errors caused by transmission from being included in the received signal and, in particular, to multi-dimensional coding.

BACKGROUND OF THE INVENTION

When information is sent from a transmitter over a channel to a receiver, the information signals are often distorted by noise and other causes. Sometimes the information signals are distorted to such an extent that the received signals do not duplicate the information sent.

In order to reduce errors in the received signals, the information is coded at the transmitter. There are two basic coding schemes: block coding and convolution coding. These coding schemes are explained in detail in a book entitled "Error Control Coding: Fundamentals and Applications" by S. Lin et al.

Simply stated, block coding introduces n-k redundant bits to a block of k bits of information to derive a coded block of n bits which is transmitted to a receiver. For binary signals, there are 2^(k) code words, each of length n, and the set is called an (n, k) block code. Convolutional coding introduces m bits from previous blocks of information, each having k bits, to derive a coded signal having n bits. The encoder is said to have a memory order of m. The set of codes is called an (n, k, m) convolutional code. The code rate is k/n.

U.S. Pat. No. 4,077,021 teaches a technique called set partitioning that assigns signal points to successive blocks of input data. More particularly, a code rate of 4 bits/2-dimensional symbol is shown. Also, a coding gain of 4 db over standard uncoded transmission is obtained. That is, noise immunity is obtained without increasing the power required for transmission. As will be described fully in the detailed description of the present invention, it is desirable to obtain a more efficient coding scheme.

SUMMARY OF THE INVENTION

In accordance with the illustrative embodiment of the present invention there is disclosed a multidimensional coder which (1) reduces the power consumed, (2) achieves a high code rate, and (3) provides an efficient scheme by low power use and low error in the received signal.

More particularly, according to one embodiment of the present invention, an information block comprising eight bits of input to the coder is converted into any one of five hundred and twelve four-dimensional code words. The eight bits are changed into an output having nine bits by retaining two input bits from the immediately preceding block and one input bit from two preceding blocks. The output is divided into two signal groups: a first group comprises five bits and a second comprises four bits.

The first group having five uncoded bits addresses any one of thirty-two (2⁵ =32) locations of a read only memory. Each location has a code word comprising four numbers, representing the coordinates of a point in four-dimensional space. The numbers appearing in the thirty-two code words include 1, -1, 3, -3, 5, and -5. These code words are shown in tables 1 and 2, included in the detailed description of the invention hereinbelow.

The second group of four bits make up a vector which determines the sign of the four-dimensional code word read from the read only memory. This scheme is equivalent to having the code word read from any page of a code book having sixteen (2⁴ =16) pages, each page having thirty-two code words entered therein.

Thus, there is disclosed a trellis code with rate of eight bits per four-dimensional symbol with a gain of 4.7 decibels over standard uncoded transmission. This 0.7 decibel increase over the aforesaid prior art code systems corresponds to improving the block error rate by a factor of 10. The signal constellation comprises five hundred twelve four-dimensional signal points, that is, each symbol has a set of four numbers which defines a signal point in four-dimensional space.

By way of comparison, first, transmission of two consecutive two-dimensional signals using one of the prior art codes with rate four bits per two-dimensional symbol would require the equivalent of 1, 024 (because 32² =1024) four-dimensional signal points. That is, the size of the code is reduced. Second, the restriction of the five hundred twelve point constellation to the first two coordinates, or to the last two coordinates, requires only a set of thirty-two signal points. This code rate of eight bits per four-dimensional symbol is suggested for data transmission rates of 9.6 kbits/sec.

In another embodiment of the present invention, a trellis code with rate twelve bits per four-dimensional symbol provides a gain of 4.9 db over standard uncoded transmission. This method is suggested for data transmission rates of 14.4 kbits/sec.

In the limit, when the number, k, of bits in a block approaches infinity, the coding gain is asymptotic to 4.9715 decibels. That is, the difference between the limiting gain and that provided with k=12 is very small.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a prior art system for transmission of encoded signals;

FIG. 2 illustrates the concept of convolutional encoders;

FIG. 3 shows possible transitions of states between two instants in time;

FIG. 4 illustrates error events and the term Euclidean distance;

FIG. 5 shows a convolutional encoder of memory order three;

FIG. 6 shows a signal constellation for uncoded transmission at the rate four bits per two dimensional symbol;

FIG. 7 shows a convolutional encoder embodying the present invention;

FIG. 8 shows a rectangular constellation for uncoded transmission at six bits per two dimensional symbol; and

FIG. 9 shows a signal constellation for trellis codes at the rate four bits per two dimensional symbol.

DETAILED DESCRIPTION

Referring to FIG. 1, there is shown a prior art system comprising a digital source 10 supplying a signal to encoder 12. The coded signal from encoder 12 is modulated by device 14 for transmission to a distant location where the signal is demodulated at device 18. The demodulated signal is thereafter decoded at device 20 and sent on to a digital sink 22. The use of encoder 12 reduces the errors caused by noise in the transmission facility 16. The present invention relates to an improvement in the aforesaid encoder 12.

It is necessary to disclose the theoretical basis for the present invention in order to fully appreciate it. Assume that an input block of k bits from a serial bit stream is first converted by a series-to-parallel converter such as device 70 in FIG. 7, such converters being well known, to an input of k parallel bits {a₁ ^(i) }, {a₂ ^(i) }, {a₃ ^(i) }, . . . , {a_(k) ^(i) } prior to entering the encoder at time i. Assume further that the output of the encoder, at time i, is x^(i) and depends not only on the present value of the input sequence but also on the previous v_(i) ≧0 bits as illustrated in FIG. 2. That is, the encoder is a convolutional encoder as well as a block encoder. If v_(j) =0 then {a_(j) ^(i) } is said to be a sequence of uncoded bits. The constraint length v is given by ##EQU1## The output of x^(i) of the encoder is a fixed function x of the (v+k) variables a₁ ^(i), . . . , a₁ ^(i-v).sbsp.1 ; a₂ ^(i), . . . , a₂ ^(i-v).sbsp.2 ; a₃ ^(i), . . . , a₃ ^(i-v).sbsp.3 ; . . . ; a_(k) ^(i), . . . , a_(k) ^(i-v).sbsp.k.

That is,

    x.sup.i =x(a.sub.1.sup.i a.sub.1.sup.i--1 . . . a.sub.1.sup.i-v.sbsp.1 ; . . . ; a.sub.k.sup.i a.sub.k.sup.i-1 . . . a.sub.k.sup.i-v.sbsp.1).

The v-tuple (a₁ ¹ a₁ ^(i-1) . . . a₁ ^(i-v).sbsp.1 ; . . . ; a_(k) ^(i) a_(k) ^(1-l) . . . a_(k) ^(i-v).sbsp.1) is the state of the encoder and there are 2^(k) states.

Referring to FIG. 3, there is shown a state transition diagram from time i to time (i=1) for a trellis code with k=3, v₁ =0, v₂ =1, and v₃ =2. Looking briefly ahead to FIG. 5, there is shown a coder, which is an application of FIG. 2, where the a₁ ^(i) sequence has no memory, that is, v₁ =0, or uncoded; where a₂ ^(i) sequence has one bit of memory, that is, v₂ =1; and, where the a₃ ^(i) sequence has two bits of memory, that is, v₃ =2. Because three bits of memory exist, there are (2³ =8) eight states for the coder. The three bits shown at time i are the bits stored for a₂ at time (i-1), that is, a₂ ^(i-1) ; for a₃ at time (i-1), that is, a₃ ^(i-1) ; and a₃ at time (i-2), that is, a₃ ^(i-) 2. An edge joins two states at time i and i+1. Each edge is double in this case, as will be explained below.

The state transition diagram can be understood by examining, for example, the transition from the state `010` at time i to a state at time i+1. Remembering that at time i the 1 in state `010` is a₃ ^(i-1), at time i+1 this bit 1 will now be a₃ ^(i-2) and can be any one of the four codes which end in a 1 : 001, 101, 011, or 111 depending on the next value of a₂ ^(i-i) and a₃ ^(i-1).

Returning to the theoretical basis, noise in the transmission channes distorts the sequence of signals from the output of the coder:

    x.sup.i =(x.sup.i1, x.sup.i2, x.sup.i3, x.sup.i4).

Then, the signal received say at decoder 20 of FIG. 1, is:

    r.sup.i =(r.sup.i1, r.sup.i2, r.sup.i3, r.sup.i4)

where r^(ij) =x^(ij) +z^(ij), the z^(ij) being the noise component. The noise samples z^(ij) are independent zero-mean Gaussion variables of variance, σ².

The Viterbi algorithm, disclosed at 61 Proceedings of the IEEE 268-278 (No. 3, March, 1973), is used to find the most likely path through the trellis given the observed sequence ∥r^(i) ∥. The path chosen will not always coincide with the correct path, but will occasionally diverge from it and remerge at a later time. This is called an error event.

An error event E of length l lasts from j to (j+1), the sequence x^(j), . . . , x.sup.(j+l-L) instead of the correct sequence x^(j), . . . , x.sup.(j+1-L). The squared Euclidean distance d², that is d² (E), between the two paths of E is given by ##EQU2## where ∥ ∥ denotes the usual Euclidean norm.

Referring to FIG. 4, there is shown an error event for which the squared Euclidean distance is ##EQU3##

The average transmitted power is given by ##EQU4##

For small noise variance σ², the minimum distance d_(min) over all error events determines the probability of error. The figure of merit for a trellis code is the normalized minimum distance stated by the ratio: ##EQU5## The bigger this ratio, the better the code. The performance of a coding scheme is measured against that of uncoded transmission at the same rate. The coding gain in decibels, db, is given by the expression: ##EQU6##

Basic to the trellis codes of the present invention disclosed hereinbelow is a rate 3/4 binary convolutional code with a total memory 3 and free distance 4. A portion of the encoder is shown in FIG. 5 which has been disclosed in the aforesaid Lin book at page 292. The three parallel input sequences a₁ ^(i), a₂ ^(i) and a₃ ^(i) determine the output sequence v^(i) =(v₁ ^(i), v₂ ^(i), v₃ ^(i), v₄ ^(i)) according to the rules:

    v.sub.1.sup.i =a.sub.1.sup.i,

    v.sub.2.sup.i =a.sub.1.sup.i +a.sub.2.sup.i +a.sub.2.sup.i-1 +a.sub.3.sup.i-1,

    v.sub.3.sup.i =a.sub.1.sup.i +a.sub.2.sup.i-1 +a.sub.3.sup.i +a.sub.3.sup.i-2, and

    v.sub.4.sup.i =a.sub.1.sup.i +a.sub.2.sup.i +a.sub.3.sup.i +a.sub.3.sup.i-2.

The bits a₂ ^(i-1), a₃ ^(i-1), and a₃ ^(i-2) describe the state of the encoder. The possible transitions between states of such an encoder is shown hereinabove in FIG. 3. The edge joining state a₂ ¹⁻¹ a₃ ^(i-1) a₃ ^(i-2) to state a₂ ^(i) a₃ ^(i) a₃ ^(i-1) is labelled with the outputs V^(i) =(v₁ ^(i), v₂ ^(i), v₃ ^(i), v₄ ^(i)) and V^(i) =(v₁ ^(i), v₂ ^(i), v₃ ^(i), v₄ ^(i)) corresponding to this transition so that

    v.sub.1.sup.i =a.sub.1.sup.i,

    v.sub.2.sup.i =a.sub.1.sup.i +a.sub.2.sup.i-1 +a.sub.2.sup.i +a.sub.3.sup.i-1,

    v.sub.3 =a.sub.1.sup.i +a.sub.2.sup.i-1 +a.sub.3.sup.i +a.sub.3.sup.i-2, and

    v.sub.4 =a.sub.1.sup.i +a.sub.2.sup.i +a.sub.3.sup.i +a.sub.3.sup.i-2.

The binary notation 0,1 is then changed to 1, -1, respectively. An edge joining two states is then labelled with a pair of vectors (w₁, w₂, w₃, w₄) and (-w₁, -w₂, -w₃, -w₄) where w_(i) =±1 and i=1, 2, 3, and 4. This defines a trellis encoder with rate 3 bits/4-dimensional symbol. The minimum squared distance of this trellis code is simply four times the free distance of the original binary convolutional code, namely 16. This is so because 0 opposite 1 contributes 1 to the free distance while 1 opposite -1 contributes 4 to the squared minimum distance.

Thus far, a trellis code at the low rate 3 bits/4-dimensional symbol was disclosed. Transmission at higher rates, say 8 bits/4-dimensional symbol or 12 bits/4-dimensional symbol requires more channel symbols.Indeed, as is readily apparent from the disclosure thus far, in order to achieve any coding gain, more symbols are needed than for uncoded transmission at the same rate.

Referring to FIG. 6, there is shown a rectangular constellation comprising sixteen (2⁴ =16) signal points for standard uncoded transmission, of binary input, at the rate of 4 bits/2-dimensional symbol. For uncoded transmission of a 4-dimensional symbol, two copies of the constellation shown in FIG. 6 are needed, yeilding 256 (16×16=256) possible signals. Using the formula developed earlier herein, the average power or energy is ##EQU7## that is, 20. Because the minimum squared distance between distinct signals is four, the figure of merit is given by the formula: ##EQU8##

For coded transmission, however, 512 signal points are used, namely, twice the signal constellation for uncoded transmission of 4-dimensional symbols. This is so because a block of eight input bits is converted to nine bits using three bits from prior blocks and 2⁹ is 512. This conversion will become clear by referring to FIG. 7, wherein is shown a stream of binary bits on lead 71 converted from serial to parallel in converter 70 and then set on via two sets of leads 73 and 51.

The first set of leads 73 carries five uncoded bits which are converted from binary form by changing a 0 to a 1 and a 1 to a -1 in known device 72 and then sent on via leads 75 to address any one of thirty-two (2⁵ =32) code words, representing signal points, from a storage device such as read only memory (ROM) 74. Because each code word defines a point in four dimensional space, four numbers are required for each code word. The numbers of the addressed code word are passed via leads 77 to multipliers 82 . . . 88. Representative signal points are shown in Table 1 hereinbelow.

                  TABLE 1                                                          ______________________________________                                          Signal PointRepresentative                                                                   Average PowerEnergy Level or                                                                ##STR1##                                           ______________________________________                                         (1111)             4       1                                                   (3111)            12       4                                                   (3311)            20       6                                                   (5111)            28       4                                                   (3331)            28       4                                                   (5311)            36       12                                                  (3333)            36       1                                                   Total number of code       32                                                  words                                                                          ______________________________________                                    

The first column of Table 1 shows the code words representative of signal points in four dimensional space. The number of permutations for each representative code word is shown in column three, giving a total of thirty-two code words stored in ROM 74. The list of thirty-two code words is obtained by permuting the coordinates of the code words in column one.

The second set of leads 51 from serial to parallel converter 70 carries three of the binary input bits to a device 50 which stores three bits from prior blocks as disclosed in detail earlier herein with reference to FIG. 5, and delivers four bits on leads 53 to a device 80, At device 80 the binary bit 0 is converted to 1 and a binary 1 is converted to a -1. The vector W of four bits w₁, w₂, w₃, and w₄ is then delivered to multipliers 82 . . . 88. The number y₁ of the accessed code word is then multiplied by w₁ from lead 81 at multiplier 82 to generate output x₁. That is, y₁ is negated if w₁ is -1 but remains unchanged if w₁ is +1. Likewise, x₂, x₃, and x₄ are generated and sent over leads 89.

Because there are four bits w₁, w₂, w₃, and w₄, and because there are two values 1 or -1 for each, together there can be sixteen (2⁴ =16) different permutations of these bits. Because there are thirty-two signal points (x₁, x₂, x₃, x₄) in the set S(w) which satisfy the requirement x_(i) ≡w_(i) (mod 4), for i=1, 2, 3, and 4, there are 512 (16×32=512) symbols in the signal constellation, because all permutations are allowed. Thus, the coding scheme of the present invention can be thought of as a code book comprising sixteen pages with thirty-two code words on each page. Each page corresponds to the vector w_(i), where i=1, 2, 3, and 4. The thirty-two code words correspond to the entries in ROM 74. The entire list of thirty-two code words in ROM 74 is shown in Table 2 hereinbelow.

                  TABLE 2                                                          ______________________________________                                         Input to ROM 74    Code Output From ROM 74                                     a.sub.4                                                                              a.sub.5                                                                               a.sub.6                                                                               a.sub.7                                                                             a.sub.8                                                                             y.sub.1                                                                              y.sub.2                                                                             y.sub.3                                                                             y.sub.4                          ______________________________________                                         1     1      1      1    1    1     1    1    1                                -1    1      1      1    1    3     1    1    1                                1     -1     1      1    1    1     3    1    1                                -1    -1     1      1    1    1     1    3    1                                1     1      -1     1    1    1     1    1    3                                -1    1      -1     1    1    3     3    1    1                                1     -1     -1     1    1    3     1    3    1                                -1    -1     -1     1    1    3     1    1    3                                1     1      1      -1   1    1     3    3    1                                -1    1      1      -1   1    1     3    1    3                                1     -1     1      -1   1    1     1    3    3                                -1    -1     1      -1   1    5     1    1    1                                1     1      -1     -1   1    1     5    1    1                                -1    1      -1     -1   1    1     1    5    1                                1     -1     -1     -1   1    1     1    1    5                                -1    -1     -1     -1   1    3     3    3    1                                1     1      1      1    -1   3     3    1    3                                -1    1      1      1    -1   3     1    3    3                                1     -1     1      1    -1   1     3    3    3                                -1    -1     1      1    -1   5     3    1    1                                1     1      -1     1    -1   5     1    3    1                                -1    1      -1     1    -1   5     1    1    3                                1     -1     -1     1    -1   3     5    1    1                                -1    -1     -1     1    -1   1     5    3    1                                1     1      1      -1   -1   1     5    1    3                                -1    1      1      -1   -1   3     1    5    1                                1     -1     1      -1   -1   1     3    5    1                                -1    -1     1      -1   -1   1     1    5    3                                1     1      -1     -1   -1   3     1    1    5                                -1    1      -1     -1   -1   1     3    1    5                                1     -1     -1     - 1  -1   1     1    3    5                                -1    -1     -1     -1   -1   3     3    3    3                                ______________________________________                                    

The set of coordinates (x₁, x₂, x₃, x₄) representing the input block of 8 bits on leads 89 is then sent on to a modulator. The present invention relates to an encoder only and therefore other equipment cooperating with the encoder is not disclosed in any detail, beyond what was disclosed earlier with reference to FIG. 1.

The distance d (A, B) between two sets of vectors A and B is given by the expression: ##EQU9## The partition into sets S(w) satisfies the following metric properties: (M1): if x, yεS(w), then ∥x-y∥² ≧16; and

(M2): is v≠w, then d² (S(v), S(w))=∥v-w∥².

To verify (M1), let x=(x₁, x₂, x₃, x₄) and y=(y₁, y₂, y₃, y₄). Then x_(i) ≠y_(i) for some i. Since x_(i) ≡y_(i) (mode 4), we have ∥x-y∥≧16. To verify (M2), let x=(x₁, x₂, x₃, x₄)εS(v), and y=(y₁, y₂, y₃, y₄)εS(w). If x_(i) ≢y_(i) (mod 4), then |x_(i) -y_(i) |² ≧4. Hence ∥x-y∥² ≧∥v-w∥² and the equality holds when x=v and y=w.

Earlier hereinabove, a trellis code with rate 3 bits/4-dimensional symbol having a minimum squared distance d_(min) ² =16 was disclosed. In order to achieve a higher transmission rate of 8 bits/4-dimensional symbol, five uncoded bits were added, obtaining an input of eight parallel sequences to the encoder in FIG. 7: {a₁ ^(i) }, {a₂ ^(i) }, {a₃ ^(i) }, . . . , {a₈ ^(i) }. The sequences {a₂ ^(i) }, {a₃ ^(i) } determine the state a₂ ^(i-1) a₃ ^(i-1) a₃ ^(i-2) of the encoder in FIG. 7. An edge joining two states that was originally labelled by the pair of vectors ±w in FIG. 3 is now labelled by the sixty-four vectors (not shown) in the set S(v) U S(-v). This is so because there are sixty-four parallel transitions between states a₂ ^(i-1) a₃ ^(i-1) a₃ ^(i-2) and a₂ ^(i) a₃ ^(i) a₃.sup. i-1 corresponding to the sixty-four possible inputs a₁ ^(i) a₄ ^(i) . . . a₈ ^(i). Furthermore, any fixed assignment of code symbol in S(v) U S(-v) to inputs a₁ ^(i) a_(4hu) i . . . a₈ ^(i) is permitted.

The properties (M1) and (M2) guarantee that the squared distance of any error event of length l is at least 16. Consider any error event in the eight state trellis of length greater than 1. If the squared distance for the low-rate code is ##EQU10## then the squared distance for the high rate code is at least ##EQU11## The property (M2) implies that the minimum squared distance of the high-rate code is at least 16. The average signal power P of the 512 point signal constellation is given by the expression: ##EQU12## Thus, ##EQU13## and the coding gain in db is: ##EQU14##

Referring to FIG. 8, there is shown a signal constellation comprising sixty-four signal points which is used for standard uncoded transmission at the rate of 6 bits/2-dimensional symbol. To transmit a 4-dimensional symbol at a rate of 12 bits/symbol, a constellation comprising two such copies are needed. The number of possible signals will be 4, 096 (64×64=4096). The average signal power P is ##EQU15## Thus, ##EQU16##

For coded transmission using three bits from prior blocks, 8, 192 (2¹³ =8192) signal points are needed. As in the 8 bits/4-dimensional symbol, the signal constellation is partitioned into sixteen sets S(w) according to congruence of the entries modulo 4. Each set S(w) will contain, however, 512 signal points, or code words. Representative signal points are listed hereinbelow in Table 3.

                  TABLE 3                                                          ______________________________________                                          Representative                                                                              Energy                                                                                   ##STR2##                                               ______________________________________                                         (1111)       4         1                                                       (3111)       12        4                                                       (3311)       20        6                                                       (5111), (3331)                                                                              28        4 + 4 = 8                                               (5311), (3333)                                                                              36        12 + 1 = 13                                             (5331)       44        12                                                      (7111), (5333), (5511)                                                                      52        4 + 4 + 6 = 14                                          (7311), (5531)                                                                              60        12 + 12 = 24                                            (7331), (5533)                                                                              68        12 + 6 = 18                                             (7333), (5551), (7511)                                                                      76        4 + 4 + 4 + 12 = 20                                     (9111), (7531), (5553)                                                                      84        4 + 24 + 4 = 32                                         (9311), (7533)                                                                              92        12 + 12 = 24                                            (9331), (7711), (7551),                                                                     100       12 + 6 + 12 + 1 = 31                                    (5555)                                                                         (7553), (9333), (9511),                                                                     108       12 + 4 + 12 + 12 = 40                                   (7731)                                                                         (9531), (7733)                                                                              116       24 + 6 = 30                                             (9533), (11111), (7751),                                                                    124       12 + 4 + 12 + 4 =  32                                   (7555)                                                                         (11311), (9711), (9551),                                                                    132       12 + 12 + 12 + 12 = 48                                  (7753)                                                                         (11331), (9731), (9553)                                                                     140       12 + 24 + 12 = 48                                       (11333), (11511), (9733),                                                                   148       4 + 12 + 12 + 6 + 4 = 38                                (7755), (7771)                                                                 (11531), (9555), (9751)                                                                     156       24 + 4 + 24 + 4 = 56                                    (7773)                                                                         (11533), (9911), (9753)                                                                     164       only 13                                                 ______________________________________                                    

In order to obtain a transmission rate of 12 bits/4-dimensional symbol it is necessary to add nine uncoded bits to the four derived bits from FIG. 5, to obtain a total of 13. There are now 1024 parallel transitions between states a₂ ^(i-1) a₃ ^(i-1) a₃ ^(i-2) and a₂ ^(i) a₃ ^(i) a₃ ^(i-1) in the eight state trellis. If the edge corresponding to this transition was originally labelled ±w, it is now labelled with the 1024 vectors in S(w) U S(-w). The metric properties (M1) and (M2) guarantee that the squared minimum distance of the high-rate code is equal to the squared mininmum distance of the low-rate code, which is 16. The average signal power is 108.625, and so the figure of merit is: ##EQU17## and the coding gain is: ##EQU18##

Summarizing the aforesaid disclosure, in order to achieve coded transmission at a rate of k bits per four dimensional signal, (k-3) uncoded bits are added to the low rate trellis code, that is, 3 bits per four dimensional symbol, as disclosed hereinabove, with reference to FIG. 3. There are 2.sup.(k-2) parallel transitions between states a₂ ^(i-1) a₃ ^(i-l) a₃ ^(i-2) and a₂ ^(i) a₃ ^(i) a₃ ^(i-1) in the eight state trellis. Relating this to FIG. 3, there are two parallel transitions between the two aforesaid states because 2.sup.(3-2) is 2.

Coded transmission requires 2.sup.(k+1) signal points. The points of the lattice (2Z+1)⁴, where (2Z +1) represents the set of odd numbers, lie in shells around the origin consisting of sixteen vectors of energy four, sixty-four vectors of energy twelve, . . . , shown summarized in Table 3. The 2^(k+1) signal points are obtained by taking all points of energy four, twelve, twenty, . . . and just enough points of a final shell to bring the total number up to 2^(k+1). The signal constellation is partitioned into sixteen sets S(w) according to congruence of the entries modulo four Each set contains 2^(k-3) signal points. Thus, when k=8, each set has thirty-two signal points (2⁸⁻³ =32) as is shown in FIG. 9. Edges in the eight state trellis originally labeled ±w are now labelled with the 2^(k-2) vectors in S(w) U S(-w). The metric properties (M1) and (M2) guarantee that the minimum squared distance of this trellis code is sixteen.

It can be shown that as k increases, that is, in the limiting case, the limiting coding gain is 10log₁₀ π=4.914 db. That is, the maximum coding gain is 4.914 db. But the coding gain for twelve bits per four dimensional symbol is 4.904 db and the coding gain for eight bits per four dimensional symbol is 4.717 db. Thus, the scheme disclosed by the present invention is an efficient method of coding. 

What is claimed is:
 1. A method for coding information comprising the steps ofseparating said information into first and second groups of signals, addressing any one of a plurality of multidimensional code words by said first group of signals, and determining the sign of each componet of said multi-dimensional code words by said second group of signals.
 2. The method of claim 1 for coding information wherein said multi-dimensional code words are four-dimensional code words.
 3. The method of claim 2 for coding information wherein said information comprises a block of eight binary bits, said first group comprises five of said eight binary bits, and said second group comprises the other three of said eight binary bits.
 4. The method of claim 3 for coding information wherein said four-dimensional code words consist of a set of thirty-two four-dimensional code words stored in a memory device and each of said four-dimensional code words consist of a subset of four numbers which represent the coordinates of a signal point in four-dimensional space.
 5. The method of claim 4 for coding information further comprising the step of converting binary 1's to -1's and binary 0's to 1's for said first group of signals prior to addressing said four-dimensional code words.
 6. The method of claim 5 for coding information further comprising the steps ofexpanding the number of bits in said second group of signals from three to four in a convolutional encoder comprising three bits of memory, and converting the binary 1's to -1's and binary 0's to 1's.
 7. The method of claim 6 further comprising the step of multiplying each of said components of said four-dimensional code word by said expanded and converted second group of signals, thereby deriving any one of five hundred and twelve encoded four-dimensional symbols for each input block of eight binary signals.
 8. The method of claim 2 for coding information wherein said information comprises a block of twelve binary bits, said first group comprises nine of said binary bits and said second group comprises the other three of said twelve binary bits.
 9. The method of claim 8 for coding information wherein said four-dimensional code words consist of a set of five hundred and twelve four-dimensional code words stored in a memory device and each of said four-dimensional code words consist of a subset of four numbers which represent the coordinates of a signal point in four-dimensional space.
 10. The method of claim 9 for coding information further comprising the step of converting binary 1's to -1's and binary 0's to 1's for said first group of signals prior to addressing said four-dimensional code words.
 11. The method of claim 10 for coding information further comprising the steps ofexpanding the number of bits in said second group of signals from three to four in a convolutional encoder comprising three bits of memory, and converting the binary 1's to -1's and binary 0's to 1's.
 12. The method of claim 11 for coding information further comprising the step of multiplying each of said components of said four-dimensional code word by said expanded and converted second group of signals, thereby deriving any one of eight thousand, one hundred and ninety-two encoded four-dimensional symbols for each input block of twelve binary signals.
 13. Apparatus for coding information comprisingmeans for converting a predetermined plurality of serial binary bits into parallel bits, said parallel bits being separated into first and second groups of signals, means for converting the binary 1's to -1's and binary 0's to 1's for said first group of signals which are then used for addressing any one of a plurality of multi-dimensional code words said code words being stored in a memory device, and said second group of signals being used for determining the sign of each component of said multi-dimensional code words after said code words are read out from said memory device.
 14. The apparatus of claim 13 wherein said multi-dimensional code words are four-dimensional code words, each code word comprising four numbers representing the coordinates of a signal.
 15. The apparatus of claim 14 comprisinga convolutional encoder which comprises means for storing a plurality of bits for expanding the number of bits in said second group of signals, by one, and means for converting the expanded bits from binary 1's to -1's and binary 0's to 1's.
 16. The apparatus of claim 15 wherein said memory device is a read only memory.
 17. The apparatus of claim 16 for coding information comprising means for multipling each component of the code words from said read only memory by said expanded and converted second group of signals to derive an encoded four-dimensional symbol for each block of information.
 18. The apparatus of claim 17 whereinsaid predetermined plurality of serial binary bits comprises a block of eight binary bits, said first group comprises five bits of said eight bits, said means for storing a plurality of bits in said convolutional encoder having a capacity for storing three bits, said second group comprises the other three of said eight binary bits, said three bits being the input to said convolutional encoder, the output from said convolutional encoder being four bits, said read only memory comprises a set of thirty-two four-dimensional code words, and said encoded symbols being any one of a signal constellation comprising five hundred and twelve four-dimensional code words.
 19. The apparatus of claim 17 whereinsaid predetermined plurality of serial binary bits comprises a block of twelve binary bits, said first group of signals comprises nine bits of said twelve binary bits, said means for storing a plurality of bits in said convolutional encoder having a capacity for storing three bits, said second group comprises the other three bits of said twelve binary bits as the input to said convolutional encoder, the output from the convolutional encoder being four bits, said read only memory comprises a set of five hundred twelve four-dimensional code words, and said encoded symbols being any one of a signal constellation comprising eight thousand, one hundred and ninety-two four-dimensional code words.
 20. Apparatus for coding an input of eight binary bits to any one of five hundred and twelve code words each code word having four numbers representing the coordinates of signal points in four-dimensional space said apparatus comprisinga read only memory comprising thirty-two of said four dimensional code words, a serial-to-parallel converter for converting a serial stream of blocks of eight binary bits into sequences of eight parallel bits, five of said eight parallel bits being used to address any one of said thirty-two code words in said read only memory after passing through a means for converting binary 1's to -1's and binary 0's to 1's, the remaining three bits of said eight parallel bits being the input to a convolutional encoder having three bits of memory, said convolutional encoder being used to expand said three bits of input to four bits of output, means for converting said four bits of output from said convolutional encoder from binary 1's to -1's and from binary 0's to 1's, and means for multiplying each component said four numbers from said read only memory by said four output bits from said convolutional encoder to derive any one of said five hundred and twelve four dimensional code words. 